The Challenges of Increasing Complexity in Semiconductor Manufacturing
The landscape of semiconductor manufacturing is evolving rapidly, driven by aggressive feature scaling and increasingly complex transistor structures. This evolution comes with a growing concern: the complexity of processes is on an upward trajectory, heightening the risk that designs may not be manufacturable with acceptable yield levels. The push for smaller features and denser layouts means that a single layer in a semiconductor device now demands significantly more process steps than ever before. Each step comes laden with a multitude of tunable parameters, all of which require careful consideration to ensure yields remain within acceptable limits.
Navigating Design for Manufacturing (DFM) Rules
To help manage design risk, chip foundries provide detailed Design for Manufacturing (DFM) rules. These rules serve as guidelines for designers, indicating which patterns are problematic and should be avoided. However, the sheer volume of DFM rules associated with leading-edge processes can easily overwhelm conventional design methodologies. When faced with this labyrinth of constraints, it might not be feasible to create a design that fulfills all foundry requirements simultaneously. In cases where fulfilling every requirement is impossible, a model may fail to converge—making it a daunting task for designers who are often pressured to ensure their solutions are both innovative and manufacturable.
Kostas Adam, vice president of engineering at Synopsys, highlights the potential of leveraging machine learning techniques, particularly neural networks, to mitigate these challenges. By augmenting or sometimes even replacing traditional compact models, these advanced techniques can assist in identifying risk-prone design patterns and elucidating the complex cause-effect relationships inherent in semiconductor design.
Power, Performance, and Area (PPA) Tradeoffs
The DFM constraints significantly influence the tradeoffs between power, performance, and area (PPA) within designs. A straightforward approach to resolving a DFM violation often simply involves increasing the spacing between affected devices, yet this approach rarely leads to optimal PPA outcomes. Achieving ambitious PPA targets often necessitates accepting a larger margin of design risk, which can translate to potential yield reductions. These intricate interdependencies are especially challenging to navigate in the early stages of process development when realistic design examples are limited. Designing effective DFM rules without adequate testing on realistic designs becomes an almost insurmountable task.
Hot Spot Detection and Synthetic Layout Generation
Identifying and addressing defect "hot spots" is an integral aspect of semiconductor manufacturing. Geng Han, a research staff member at IBM Research, emphasized during this year’s SPIE Advanced Lithography and Patterning conference that the root causes of these hot spots often arise from interactions between layers and process steps. Traditional process development test vehicles can be limited and time-consuming, leaving many potential issues unidentified. Han’s innovative solution involves utilizing synthetic layout generation to complement traditional test vehicles.
By employing a guided machine learning model, test patterns can be generated that adhere strictly to proposed design rules. These synthetic layouts can be tailored to target specific layout densities and types of line ends, circumventing the need for electronic functionality. Simulation through lithography models allows for the identification of patterns most likely to yield defects, ultimately refining processes and updating design rules.
Iterative Optimization of Design Parameters
As Jinah Kim, a process integration engineer at Samsung, pointed out, optimizing a design’s PPA is inherently an iterative process. Designers are required to make manual adjustments to parameters, execute the place-and-route (P&R) process, and assess the outcomes. For example, evaluating 50 different design conditions in an 8,000 square micron block could demand an exhausting 1,200 CPU hours. However, Samsung’s innovative approach seeks to integrate PPA and yield considerations in parallel, drastically reducing computational time.
Utilizing Cadence’s Cerebrus, an AI-driven chip design automation tool, designers can set foundational parameters like power and leakage based on specific goals. This strategy enables the training of a machine learning model that yields designs meeting predetermined PPA targets. Consequently, when inconsistencies are found, Cerebrus generates new design scenarios that comply with proposed DFM rules—yielding a staggering reduction in evaluation time from 1,200 CPU hours to just 90 hours.
Machine Learning for DFM Violations
Lynn Wang, a principal member of the technical staff at GlobalFoundries, recognized the challenge posed by the extensive range of DFM violations. Traditional methods of fixing these issues via P&R tools often fall short given the overwhelming volume of potential discrepancies. In response, her team developed a pattern library through machine learning, grouping similar geometric features from reference designs and associating them with optimized solutions. When incorporated into the P&R hotspot repair tool, this library enabled the automatic resolution of 81% of DFM violations, demonstrating a remarkable 50-fold increase in fixing efficiency compared to conventional rerouting methods.
Defect Prediction via Post-Etch Features
Moreover, Jonathan Ho from AMD pointed out that predicting defect hot spots through design polygons alone frequently results in a surplus of false positives. Analyzing the post-etch feature shapes—which are reflective of the cumulative effects of various processes—has proven to be more reliable. AMD, in partnership with Siemens EDA, applied a reinforcement learning model to correlate design patterns with defect-prone patterns known from physical silicon. This process enhances defect prediction accuracy significantly by backing it with the actual manufacturing experience.
Maintaining Yield Over Time
As devices transition from design to production, achieving the anticipated yield can introduce further complexities. The dynamic nature of manufacturing processes involves continual evolution, where equipment degradation and aging process chemicals can further complicate yield outcomes. Taekwon Jee, CEO of SemiAI, has taken strides in this domain by establishing a framework capturing common issues alongside historical fixes. Using a proprietary digital twin tool called PRISM, his team collects and annotates process sensor data, allowing the identification of causal relationships among variables through advanced neural networks and transformer models.
Through constructing a comprehensive database linking past issues with current sensor data, SemiAI’s technology can predict potential failures and automatically suggest fixes—a notable achievement in optimizing yield. However, Jee emphasizes that human oversight remains crucial, as not every suggested solution addresses the underlying problem effectively.
Rethinking AI in Industrial Processes
In recent years, the dialogue surrounding artificial intelligence (AI) has gained momentum, especially in light of tools like ChatGPT capturing public attention. While opinions vary widely on the implications of AI technologies, it is essential to recognize that machine learning tools are not merely buzzwords. They are crucial in handling the substantial amounts of data generated in modern industrial processes, helping automate and enhance many aspects of semiconductor design and manufacturing.
As we look ahead, the integration of machine learning into semiconductor design processes will likely continue to redefine how the industry addresses the inherent complexities associated with DFM, yield optimization, and defect prediction. The opportunities for innovation are immense, presenting both challenges and compelling advancements in the pursuit of manufacturing excellence.